The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.
As a part of the semiconductor fabrication, a multilayered interconnect structure may be formed. Among other things, the interconnect structure contains metal lines and vias/contacts to provide electrical connections to transistor elements such as gate, source, and drain. The metal lines and vias are electrically insulated from one another by an interlayer dielectric (ILD) material. Existing semiconductor fabrication technologies may use silicon oxycarbide to form a part of the ILD. However, using silicon oxycarbide to form the ILD may lead to trapped voids in the ILD as well as increased resistivity due to undesirable oxidation. Consequently, semiconductor device performance is degraded.
Therefore, while conventional methods and materials for forming the ILD have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.